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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS21564-SP PS21564-SP
TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE
PS21564-SP
INTEGRATED POWER FUNCTIONS
600V/15A low-loss 5th generation IGBT inverter bridge for three phase DC-to-AC power conversion. Open emitter type.
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
* * * * * For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-leg IGBT) or a UV fault (Lower-side supply). Input interface : 3,5V line CMOS/TTL compatible. (High Active) UL Approved : Yellow Card No. E80276
APPLICATION AC100V~200V inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
Dimensions in mm
TERMINAL CODE
1.778 x 26 (=46.228) 1.778 0.15 A D
HEAT SINK SIDE 3.556 (2.056)
(0.278) (0.5)
(R0
29 30
Type name , Lot No.
3.3
(17.6) 17.4
28 27 26 25 24 23 22 21 20 19 18 16 17
15 13 14
12 10 11
987
654
321
(2 DEPTH 2)
3.556
TERMINAL
.75
)
15.25
(22.1) (17.6) 17.4
B
B
35
1.75
1.2
37 36 35
34
33
32
31
1.2
(1.5)
PCB PATTERN SLIT (ex. PCB LAYOUT) (1) (1.5) DETAIL A
Note1)
0.5
2.54
C 0.8 0.5
(0.05)
(0.7)
(0.05)
(1)
3.3 B-B
0.8
5
9
HEAT SINK SIDE
DETAIL C (36 TERMINAL)
(0~5)
All outer lead terminals are with Pb-free solder plating.
DETAIL D
Note 1 : In order to get enough creepage distance between the terminals, please take some countermeasure such as a slit on PCB.
(1.5)
(41) 42 0.15 49
NO SOLDER PLATING ON BOTH LEAD SIDE
6.7 2.54
7.62
7.62
7.62
1.25 2.5
(3.8)
0.8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
VUFS (UPG) VUFB VP1 (COM) UP VVFS (VPG) VVFB VP1 (COM) VP VWFS (WPG) VWFB VP1 (COM) WP (UNG) VNO UN VN WN FO CFO CIN VNC VN1 (WNG) (VNG) P U V W NU NV NW
30.5
0.5
4.5
(6.5) (3.5)
Jul. 2005
MITSUBISHI SEMICONDUCTOR
PS21564-SP
TRANSFER-MOLD TYPE INSULATED TYPE
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCC VCC(surge) VCES IC ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-NU, NV, NW Applied between P-NU, NV, NW Tf = 25C Tf = 25C, less than 1ms Tf = 25C, per 1 chip (Note 1) Ratings 450 500 600 15 30 22.2 -20~+125 Unit V V V A A W C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ Tf 100C) however, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ Tf 100C).
CONTROL (PROTECTION) PART
Symbol VD VDB VIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VNC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Applied between UP, VP, WP, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings 20 20 -0.5~VD+0.5 -0.5~VD+0.5 1 -0.5~VD+0.5 Unit V V V V mA V
TOTAL SYSTEM
Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature Tf Tstg Storage temperature Viso Isolation voltage Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125C, non-repetitive, less than 2 s (Note 2) 60Hz, Sinusoidal, 1 minute, All connected pins to heat-sink plate Ratings 400 -20~+100 -40~+125 2500 Unit V C C Vrms
Note 2 : Tf measurement point
Al Board Specification : Dimensions : 10010010mm, Finishing : 12s, Warp : -50~100m
Control Terminals
FWDi Chip 18mm 16mm Al Board Groove IGBT Chip NWVUP Temperature measurement point (inside the AI board) Power Terminals
DIP-IPM
Temperature measurement point (inside the AI board)
Silicon-grease should be applied evenly with a thickness of 100~200m
Jul. 2005
MITSUBISHI SEMICONDUCTOR
PS21564-SP
TRANSFER-MOLD TYPE INSULATED TYPE
THERMAL RESISTANCE
Symbol Rth(j-f)Q Rth(j-f)F Parameter Junction to case thermal resistance (Note 3) Condition Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Min. -- -- Limits Typ. -- -- Max. 4.5 6.5 Unit C/W C/W
Note 3: Grease with good thermal conductivity should be applied evenly with about +100m~+200m on the contacting surface of DIP-IPM and heat-sink.
ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWD forward voltage Condition VD = VDB = 15V IC = 15A, Tj = 25C VIN = 5V IC = 15A, Tj = 125C Tj = 25C, -IC = 15A, VIN = 0V VCC = 300V, VD = VDB = 15V IC = 15A, Tj = 125C, VIN = 0 5V Inductive load (upper-lower arm) Tj = 25C Tj = 125C Min. -- -- -- 0.60 -- -- -- -- -- -- Limits Typ. 1.45 1.55 1.50 1.20 0.30 0.40 1.50 0.50 -- -- Max. 1.95 2.05 2.00 1.80 -- 0.60 2.10 0.80 1 10 Unit V V s s s s s mA
Switching times
Collector-emitter cut-off current
VCE = VCES
CONTROL (PROTECTION) PART
Symbol Parameter Condition VD = VDB = 15V Total of VP1-VNC, VN1-VNC VIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VD = VDB = 15V Total of VP1-VNC, VN1-VNC VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VSC = 0V, FO circuit pull-up to 5V with 10k VSC = 1V, IFO = 1mA Tf = -20~100C, VD = 15V (Note 4) VIN = 5V Trip level Reset level Tj 125C Trip level Reset level CFO = 22nF (Note 5) Min. -- -- -- -- 4.9 -- 0.45 1.0 10.0 10.5 10.3 10.8 1.0 2.1 0.8 Limits Typ. -- -- -- -- -- -- -- 1.5 -- -- -- -- 1.8 2.3 1.4 Max. 5.00 0.40 7.00 0.55 -- 0.95 0.52 2.0 12.0 12.5 12.5 13.0 -- 2.6 2.1 Unit
ID
Circuit current
mA
V VFOH Fault output voltage V VFOL V VSC(ref) Short circuit trip level mA Input current IIN V UVDBt V Control supply under-voltage UVDBr protection V UVDt V UVDr ms Fault output pulse width tFO V ON threshold voltage Vth(on) Applied between UP, VP, WP-VNC, UN, VN, WN-VNC V OFF threshold voltage Vth(off) Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the current rating. 5 : Fault signal is asserted corresponding to a short circuit or lower side control supply under-voltage failure. The fault output pulse width tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 10-6 tFO [F].
Jul. 2005
MITSUBISHI SEMICONDUCTOR
PS21564-SP
TRANSFER-MOLD TYPE INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter Mounting torque Weight Heat-sink flatness Mounting screw : M3 Condition Recommended : 0.78 N*m (Note 6) Min. 0.59 -- -50 Limits Typ. -- 20 -- Max. 0.98 -- 100 Unit N*m g m
Note 6: Measurement point of heat-sink flatness
+-
Measurement location
3mm
Heat-sink side - + Heat-sink side
RECOMMENDED OPERATION CONDITIONS
Symbol VCC VD VDB VD, VDB tdead fPWM IO PWIN(on) Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Allowable r.m.s. current Condition Applied between P-NU, NV, NW Applied between VP1-VNC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS For each input signal, Tf 100C Tf 100C, Tj 125C VCC = 300V, VD = VDB = 15V, fPWM = 5kHz P.F = 0.8, sinusoidal output Tf 100C, Tj 125C (Note 7) fPWM = 15kHz (Note 8) 200 VCC 350V, Below rated current 13.5 VD 16.5V, 13.0 VDB 18.5V, Between rated current and 1.7 times of rated current -20C Tf 100C, N-line wiring inductance less than Between 1.7 times and 10nH (Note 9) 2.0 times of rated current between VNC-NU, NV, NW (including surge) Recommended value Min. Typ. Max. 0 400 300 13.5 16.5 15.0 13.0 18.5 15.0 -1 1 -- 2.0 -- -- -- 20 -- -- -- 0.3 0.5 2.0 2.6 -- -- -- -- -- -- 7.5 Arms 4.8 -- -- -- -- 5.0 V s Unit V V V V/s s kHz
PWIN(off)
Allowable minimum input pulse width
-5.0 -- Note 7 : The allowable r.m.s. current value depends on the actual application conditions. 8 : The input pulse width less than PWIN(on) might make no response. 9 : IPM might not work properly or make response for the input signal with OFF pulse width less than PWIN(off). Please refer to Fig.5.
VNC
VNC variation
Jul. 2005
MITSUBISHI SEMICONDUCTOR
PS21564-SP
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 2 THE DIP-IPM INTERNAL CIRCUIT
VUFB VUFS VP1 UP
HVIC1
VCC VB HO VS
DIP-IPM
P IGBT1 Di1
IN COM
U
VVFB VVFS VP1 VP
HVIC2
VCC VB HO VS
IGBT2
Di2
IN COM
V
VWFB VWFS VP1 VP
HVIC3
VCC VB HO VS
IGBT3
Di3
IN COM
W IGBT4 Di4
LVIC
UOUT
VN1
VCC
NU IGBT5 Di5
Fo
Fo
VOUT
NV
UN VN WN
UN VN WN VNO CIN WOUT
IGBT6
Di6
NW
VNO CIN CFO
VNC
GND
CFO
Jul. 2005
MITSUBISHI SEMICONDUCTOR
PS21564-SP
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 3 TIMING CHART OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the FO signal is set by the external capacitor CFO. a6. Input "L" : IGBT OFF. a7. Input "H" : IGBT ON. a8. IGBT OFF in spite of input "H".
Lower-arms control input Protection circuit state SET
a6 a7
RESET
Internal IGBT gate a2 a1 Output current Ic Sense voltage of the shunt resistor SC
a3
a4 a8 SC reference voltage
CR circuit time constant DELAY Error output Fo a5
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rises : After the voltage level reaches UVDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT OFF in spite of control input condition. b5. FO operation starts. b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDr
RESET
SET
RESET b6
Control supply voltage VD
b1
UVDt
b3 b4
b2 Output current Ic
b7
Error output Fo
b5
Jul. 2005
MITSUBISHI SEMICONDUCTOR
PS21564-SP
TRANSFER-MOLD TYPE INSULATED TYPE
[C] Under-Voltage Protection (Upper-arm, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UVDBt). c4. IGBT OFF in spite of control input condition, but there is no FO signal output. c5. Under voltage reset (UVDBr). c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDBr Control supply voltage VDB
RESET
SET
RESET
c1
UVDBt
c5 c3 c4 c6
c2 Output current Ic High-level (no fault output) Error output Fo
Fig. 4 RECOMMENDED CPU I/O INTERFACE CIRCUIT
5V line
10k
DIP-IPM
UP,VP,WP,UN,VN,WN
MCU
Fo VNC(Logic)
Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the wiring impedance of the printed circuit board. The DIP-IPM input section integrates a 2.5k (min) pull-down resistor. Therefore, when using an external filtering resistor, pay attention to the turn-on threshold voltage.
Fig. 5 WIRING CONNECTION OF SHUNT RESISTOR
DIP-IPM
Wiring inductance should be less than 10nH. Equivalent to the inductance of a copper pattern with length=17mm, width=3mm, and thickness=100m
VNC VNO
NU NV NW
Shunt resistor Please make the GND wiring connection of shunt resistor to the VNO, VNC terminal as close as possible.
Jul. 2005
MITSUBISHI SEMICONDUCTOR
PS21564-SP
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 6 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE
C1:Tight tolerance temp-compensated electrolytic type
C2 C1
C2,C3: 0.22~2F R-category ceramic capacitor for noise filtering
VUFB VUFS VP1 HVIC1
VCC VB HO VS
DIP-IPM
P
C3
UP
IN COM
U
C2 C1
VVFB VVFS VP1 HVIC2
VCC IN COM VB HO VS
C3
VP V
C2 C1
VWFB VWFS VP1 HVIC3
VCC VB HO VS
M
Note 1 : To prevent the input signals oscillation, the wiring of each input should be as short as possible. (Less than 2cm) 2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open drain type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 10k resistor. 4 : FO output pulse width is determined by the external capacitor between CFO and VNC terminals (CFO). (Example : CFO = 22 nF tFO = 1.8 ms (typ.)) 5 : The logic of input signal is high-active. The DIP-IPM input signal section integrates a 2.5k (min) pull-down resistor. Therefore, when using external filtering resistor, care must be taken to satisfy the turn-on threshold voltage requirement. 6 : To prevent malfunction of protection, the wiring of A, B, C should be as short as possible. 7 : Please set the C5R1 time constant in the range 1.5~2s. 8 : Each capacitor should be located as nearby the pins of the DIP-IPM as possible. 9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 pins should be as short as possible. Approximately a 0.1~0.22F snubber capacitor between the P-N1 pins is recommended. 10 : To prevent ICs from surge destruction, it is recommended to insert a Zener diode (24V, 1W) between each control supply terminals. 11 : The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.45V to max.0.52V). 12 : OR logic output level should be set up the same rating of short circuit trip level (Vsc(ref): min.0.45V to max.0.52V). Jul. 2005
CONTROLLER
5V line 15V line
C3
WP
IN COM
W
LVIC
UOUT
VN1
VCC C3 VOUT
NU
NV UN VN WN Fo VNC
UN VN WN Fo GND VNO CIN CFO WOUT
C NW
Too long wiring here might cause short-circuit.
CFO C4(CFO)
CIN
VNO
If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction.
A + B R1 Vref C5 B R1 Vref C5 B R1 Vref C5 N1
Shunt resistors
Long GND wiring here might generate noise to input and cause IGBT malfunction.
OR Logic
+ + -
Comparator
External protection circuit

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